l4-hackers

l4-hackers@os.inf.tu-dresden.de

2827 discussions

Using l4re in loadable modules of L4Linux
by Haohui Mai 13 Feb '13

13 Feb '13

Hi folks, I'm building a loadable module of L4Linux. The module calls l4re_rm_alloc() / l4re_rm_attach() to allocate shared memory. Because the symbols l4re_rm_attach_srv / l4re_utils_cap_alloc / l4re_ma_alloc_srv are not exported to the modules, I exported them using EXPORT_SYMBOL(). The module, however, still fails to load, complaining about that these symbols cannot be found. Is there a way to export these symbols so that loadable modules can use L4Re? Thanks very much! ~Haohui

2 1

Debug: how to enumerate all kernel objects
by Евгений Федотов 07 Feb '13

07 Feb '13

Hello, L4 Hackers! My question is: How to retrieve all kernel object list (threads, tasks, IRQs, Gates) in non-interactive way? Since Fiasco JDB stores the full list of objects, is there any l4_invoke_debugger call to retrieve object information from order number or ID? Best regards, Eugene.

2 1

About JDB non-interactive commands
by Евгений Федотов 04 Feb '13

04 Feb '13

Hello, L4 Hackers! From JDB manual I found that JDB supports non-interactive commands such as: enter_kdebug("*#I*IR+"); //enable IPC logging Does it work in other than x86 architectures, e.g.. Fiasco on ARM? Best regards, Eugene.

2 1

Fiasco.OC: question regarding l4_ipc_wait() and l4_ipc_reply_and_ipc_wait().
by Сергей Грехов 01 Feb '13

01 Feb '13

Hello, L4Hackers! I have several questions about two IPC: l4_ipc_wait() and l4_ipc_reply_and_ipc_wait(). 1) Is there any way to know on the receive side who had sent the IPC we have catched with l4_ipc_wait()? One of the ways if to enable IPC logging in JDB. But the problem is that trace usually consist of several thousands of IPCs and I need only one. Filtering helps a bit, but still it takes much more time to find needed info. 2) According to the description of l4_ipc_reply_and_ipc_wait() in header file: "A message is sent to the previous caller using the implicit reply capability. Afterwards the invoking thread waits for a message from any source." The question is what events/things/whatever updates this implicit reply capability and what will happen if this capability is invalid? And one more general question. Is there any documentation on JDB? -- Best regards, Sergey S. Grekhov

2 1

[OT] Berlin based Trust2Core GmbH searching for L4 developers
by Michael Voigt 31 Jan '13

31 Jan '13

Hey L4 hackers, As you may already know, recently a company called Trust2Core GmbH was founded in Berlin, which is heavily involved in the L4 microkernel business. This being the L4 hackers list, it might be of interest for you that Trust2Core is currently intensively seeking for employees with L4 and microkernel related skills. If that sounds interesting to you, please do not hesitate to have a look here <http://jobsuche.monster.de/Jobs/Trust2Core-GmbH_6?re=106> to obtain further information and apply ;). Kind regards, Michael -- Michael Voigt -Software Expert- Trust2Core <http://www.trust2core.de> Trust2Core GmbH Kurfürstendamm 22, D-10719 Berlin (Neues Kranzlereck) Phone: +49-30-652 136 152 Fax: +49-30-652 136 177 michael.voigt(a)trust2core.de Leadership in software virtualization technologies on consumer hardware platforms. Enabling the trusted path to user for highest security @ maximum fun! Trust2Core GmbH Geschäftsführung: Robert Butz (CEO), Melanie Tillmann (CFO) Handelsregister: Amtsgericht Bonn HRB 19360 Sitz der Gesellschaft: Bonn Notice: This transmittal and/or attachments may be privileged or confidential. It is intended solely for the addressee named above. Any dissemination, or copying is strictly prohibited. If you received this transmittal in error, please notify us immediately by reply and immediately delete this message and all its attachments. Thank you.

1 0

[OT] Berlin based Trust2Core GmbH searching for L4 developers
by Michael Voigt 31 Jan '13

31 Jan '13

1 0

Fiasco.OC interrupt handling
by Daniel Waddington 29 Jan '13

29 Jan '13

Hi, I'm looking into the interrupt handling in Fiasco.OC r.40 (x86/amd64). Browsing the code, it appears that the IDT only gets set up on CPU 0 and therefore on a multicore platform all interrupt handling from the kernel's perspective is from core 0. Of course the user-level handlers themselves may be elsewhere. Do I have this correct or am I misunderstanding? Thanks, Daniel

2 2

Re: Error during the "ned" package build (svn revision 42)
by ggasnier31＠free.fr 29 Jan '13

29 Jan '13

On Fri, 25 Jan 2013 00:09:55 +0100, Adam Lackorzynski wrote: >On Thu Jan 24, 2013 at 22:30:36 +0100, ggasnier31(a)free.fr wrote: >> I got the following error building the "ned" package for ARM architecture (Cortex-A9, Pandaboard). >> I use the last Linaro toolchain "gcc-linaro-arm-linux-gnueabihf-4.7-2012.12-20121214_linux". >> >> make[4]: Leaving directory `/home/repository/L4.kernel/fiasco/src/l4/ArmBuild/pkg/ned/server/src/OBJ-arm_armv7a-l4f' >> make[4]: Entering directory `/home/repository/L4.kernel/fiasco/src/l4/ArmBuild/pkg/ned/server/src/OBJ-arm_armv7a-l4f' >> make[4]: *** No rule to make target `ned.lua.bin.o', needed by `ned'. Stop. >This is strange because there is a rule for that file. ned.lua should be >in the srcdir of l4/pkg/ned/server/src? Which make version? The file ned.lua is in the l4/pkg/ned/server/src directory and the make version is 3.81 Guillaume GASNIER

2 1

Fiasco.OC performance issues
by Sebastian Sumpf 29 Jan '13

29 Jan '13

Hi L4 hackers, I recently upgraded Fiasco.OC to SVN revision 42 and experience some pretty severe performance degradation compared to revision 40 on the Pandaboard (SMP). It seems that 'simga0' and the root task stall for 5 to 10 seconds during boot up. I tracked the issue down to be caused by the initial mapping operations, especially our root task maps all the available memory during bootstrap. Within the kernel the 'Context::xcpu_tlb_flush' is called for each mapping. The function sends an IPI (to CPU1 which is idle) and then waits for an IPI in order to signal the end of the operation. The whole operation seems to have gotten slower compared to revision 40, but I could not find many differences in the IPI-handling code. Do you have any ideas or suggestions what could cause the delay (maybe scheduling changes) and how to fix it? Thanks, Sebastian -- Sebastian Sumpf Genode Labs http://www.genode-labs.com · http://genode.org Genode Labs GmbH · Amtsgericht Dresden · HRB 28424 · Sitz Dresden Geschäftsführer: Dr.-Ing. Norman Feske, Christian Helmuth

2 3

Re: Launching NOVA on QEMU
by Alexander Boettcher 26 Jan '13

26 Jan '13

Hello, try using a cpu model which is capable emulating vmx/svm. qemu -cpu ? and you get all models. qemu -cpu phenom ... works well for me. Cheers, Alex. oleg <g6kl9-07(a)yandex.ru> schrieb: >_______________________________________________ >l4-hackers mailing list >l4-hackers(a)os.inf.tu-dresden.de >http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers

2 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

l4-hackers