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Fiasco.OC: question regarding l4_ipc_wait() and l4_ipc_reply_and_ipc_wait().
by Сергей Грехов 31 Jan '13

31 Jan '13

Hello, L4Hackers! I have several questions about two IPC: l4_ipc_wait() and l4_ipc_reply_and_ipc_wait(). 1) Is there any way to know on the receive side who had sent the IPC we have catched with l4_ipc_wait()? One of the ways if to enable IPC logging in JDB. But the problem is that trace usually consist of several thousands of IPCs and I need only one. Filtering helps a bit, but still it takes much more time to find needed info. 2) According to the description of l4_ipc_reply_and_ipc_wait() in header file: "A message is sent to the previous caller using the implicit reply capability. Afterwards the invoking thread waits for a message from any source." The question is what events/things/whatever updates this implicit reply capability and what will happen if this capability is invalid? And one more general question. Is there any documentation on JDB? -- Best regards, Sergey S. Grekhov

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[OT] Berlin based Trust2Core GmbH searching for L4 developers
by Michael Voigt 31 Jan '13

31 Jan '13

Hey L4 hackers, As you may already know, recently a company called Trust2Core GmbH was founded in Berlin, which is heavily involved in the L4 microkernel business. This being the L4 hackers list, it might be of interest for you that Trust2Core is currently intensively seeking for employees with L4 and microkernel related skills. If that sounds interesting to you, please do not hesitate to have a look here <http://jobsuche.monster.de/Jobs/Trust2Core-GmbH_6?re=106> to obtain further information and apply ;). Kind regards, Michael -- Michael Voigt -Software Expert- Trust2Core <http://www.trust2core.de> Trust2Core GmbH Kurfürstendamm 22, D-10719 Berlin (Neues Kranzlereck) Phone: +49-30-652 136 152 Fax: +49-30-652 136 177 michael.voigt(a)trust2core.de Leadership in software virtualization technologies on consumer hardware platforms. Enabling the trusted path to user for highest security @ maximum fun! Trust2Core GmbH Geschäftsführung: Robert Butz (CEO), Melanie Tillmann (CFO) Handelsregister: Amtsgericht Bonn HRB 19360 Sitz der Gesellschaft: Bonn Notice: This transmittal and/or attachments may be privileged or confidential. It is intended solely for the addressee named above. Any dissemination, or copying is strictly prohibited. If you received this transmittal in error, please notify us immediately by reply and immediately delete this message and all its attachments. Thank you.

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[OT] Berlin based Trust2Core GmbH searching for L4 developers
by Michael Voigt 31 Jan '13

31 Jan '13

Hey L4 hackers, As you may already know, recently a company called Trust2Core GmbH was founded in Berlin, which is heavily involved in the L4 microkernel business. This being the L4 hackers list, it might be of interest for you that Trust2Core is currently intensively seeking for employees with L4 and microkernel related skills. If that sounds interesting to you, please do not hesitate to have a look here <http://jobsuche.monster.de/Jobs/Trust2Core-GmbH_6?re=106> to obtain further information and apply ;). Kind regards, Michael -- Michael Voigt -Software Expert- Trust2Core <http://www.trust2core.de> Trust2Core GmbH Kurfürstendamm 22, D-10719 Berlin (Neues Kranzlereck) Phone: +49-30-652 136 152 Fax: +49-30-652 136 177 michael.voigt(a)trust2core.de Leadership in software virtualization technologies on consumer hardware platforms. Enabling the trusted path to user for highest security @ maximum fun! Trust2Core GmbH Geschäftsführung: Robert Butz (CEO), Melanie Tillmann (CFO) Handelsregister: Amtsgericht Bonn HRB 19360 Sitz der Gesellschaft: Bonn Notice: This transmittal and/or attachments may be privileged or confidential. It is intended solely for the addressee named above. Any dissemination, or copying is strictly prohibited. If you received this transmittal in error, please notify us immediately by reply and immediately delete this message and all its attachments. Thank you.

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Fiasco.OC interrupt handling
by Daniel Waddington 29 Jan '13

29 Jan '13

Hi, I'm looking into the interrupt handling in Fiasco.OC r.40 (x86/amd64). Browsing the code, it appears that the IDT only gets set up on CPU 0 and therefore on a multicore platform all interrupt handling from the kernel's perspective is from core 0. Of course the user-level handlers themselves may be elsewhere. Do I have this correct or am I misunderstanding? Thanks, Daniel

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Re: Error during the "ned" package build (svn revision 42)
by ggasnier31＠free.fr 28 Jan '13

28 Jan '13

On Fri, 25 Jan 2013 00:09:55 +0100, Adam Lackorzynski wrote: >On Thu Jan 24, 2013 at 22:30:36 +0100, ggasnier31(a)free.fr wrote: >> I got the following error building the "ned" package for ARM architecture (Cortex-A9, Pandaboard). >> I use the last Linaro toolchain "gcc-linaro-arm-linux-gnueabihf-4.7-2012.12-20121214_linux". >> >> make[4]: Leaving directory `/home/repository/L4.kernel/fiasco/src/l4/ArmBuild/pkg/ned/server/src/OBJ-arm_armv7a-l4f' >> make[4]: Entering directory `/home/repository/L4.kernel/fiasco/src/l4/ArmBuild/pkg/ned/server/src/OBJ-arm_armv7a-l4f' >> make[4]: *** No rule to make target `ned.lua.bin.o', needed by `ned'. Stop. >This is strange because there is a rule for that file. ned.lua should be >in the srcdir of l4/pkg/ned/server/src? Which make version? The file ned.lua is in the l4/pkg/ned/server/src directory and the make version is 3.81 Guillaume GASNIER

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Fiasco.OC performance issues
by Sebastian Sumpf 28 Jan '13

28 Jan '13

Hi L4 hackers, I recently upgraded Fiasco.OC to SVN revision 42 and experience some pretty severe performance degradation compared to revision 40 on the Pandaboard (SMP). It seems that 'simga0' and the root task stall for 5 to 10 seconds during boot up. I tracked the issue down to be caused by the initial mapping operations, especially our root task maps all the available memory during bootstrap. Within the kernel the 'Context::xcpu_tlb_flush' is called for each mapping. The function sends an IPI (to CPU1 which is idle) and then waits for an IPI in order to signal the end of the operation. The whole operation seems to have gotten slower compared to revision 40, but I could not find many differences in the IPI-handling code. Do you have any ideas or suggestions what could cause the delay (maybe scheduling changes) and how to fix it? Thanks, Sebastian -- Sebastian Sumpf Genode Labs http://www.genode-labs.com · http://genode.org Genode Labs GmbH · Amtsgericht Dresden · HRB 28424 · Sitz Dresden Geschäftsführer: Dr.-Ing. Norman Feske, Christian Helmuth

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Re: Launching NOVA on QEMU
by Alexander Boettcher 26 Jan '13

26 Jan '13

Hello, try using a cpu model which is capable emulating vmx/svm. qemu -cpu ? and you get all models. qemu -cpu phenom ... works well for me. Cheers, Alex. oleg <g6kl9-07(a)yandex.ru> schrieb: >_______________________________________________ >l4-hackers mailing list >l4-hackers(a)os.inf.tu-dresden.de >http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers

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Launching NOVA on QEMU
by oleg 25 Jan '13

25 Jan '13

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About java support on L4linux
by Wajidali Whowe 24 Jan '13

24 Jan '13

Dear all, I have some applications written in Java and running without any problem on my local computer, where I have off course (openjdk) support. I wanted to run these applications on one of my L4linux instances where I may only have "jamvm" (an embedded version of java, which is provided for buildroot environment) Till now I booted L4linux only with ramdisks and off course for a full Java support, which might be provided for bigger systems, it would not be possible to create ramdisks. (For instance for Ubuntu or debian or Voyage... ) Do you have any suggestion on this issue? Best Regards,

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accessing msrs
by Ryan Brown 16 Jan '13

16 Jan '13

How does fiasco.oc handle accessing intel model specific registers? Is there any way to access these from user space or does this have to happen in the kernel? Specifically I'd like to access the paravirtualized clock when running under kvm.

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