- l4-hackers - example.com Site

exec()
by teclis High Elf 23 Oct '14

23 Oct '14

Could some one please point me to or give me example code to do the L4Re equivalent of UNIX exec(), spawn a new process? thanks

3 2

dynamic loading
by teclis High Elf 21 Oct '14

21 Oct '14

Does L4Re support dynamic loading? Is there an elf loader or shell? If so how do I do it? I want to run directly with L4Re. No l4linux. thanks

4 4

SMP for L4Linux on i.MX6
by Uwe Geuder 19 Oct '14

19 Oct '14

Hi! We have an i.MX6 quadcore SoC and obviously we would like to use more than 1 core in L4Linux. So far I have not succeeded to do that. jdb shows 4 CPUs and some tasks on different ones, so I assume our Fiasco configuration supports SMP. Still all L4Linux tasks are on the same one and CPU stress testing shows clearly that only 1 CPU is in use. >From an earlier posting on this list I found the L4.Proto.Scheduler configuration for ned. I tried various options but there was no effect, L4Linux user space runs on 1 core only. -- CPUs 1 + 2 -- scheduler = L4.Env.user_factory:create(L4.Proto.Scheduler, 0x18, 0x8, 6), -- maybe no mask means all CPUs? scheduler = L4.Env.user_factory:create(L4.Proto.Scheduler, 0x18, 0x8), Next I looked at our L4Linux configuration and indeed CONFIG_SMP was not set. However after enabling it the kernel does no longer build: arch/arm/mach-imx/built-in.o: In function `imx_smp_prepare': /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/platsmp.c:79: undefined reference to `scu_enable' /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/platsmp.c:79: undefined reference to `scu_enable' arch/arm/mach-imx/built-in.o: In function `imx_smp_init_cpus': /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/platsmp.c:71: undefined reference to `scu_get_core_count' arch/arm/mach-imx/built-in.o: In function `v7_secondary_startup': /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/headsmp.S:33: undefined reference to `v7_invalidate_l1' /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/headsmp.S:35: undefined reference to `secondary_startup' The SCU http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CDDEHD… has to do with cache coherency, obviously important on SMP. The SCU code is in native ARM, but not in L4 ARM. I somehow have the feeling just copying it is not enough. Does the virtual CPU seen by L4Linux need to control/use the SCU or is that something made completely transparent by the virtual cpu offered by L4? v7_secondary_startup code is behind !defined(CONFIG_L4). The code does a lot of MMU initializion stuff, so my guess is this cannot worked unchanged under L4. So the question is: Is SMP for i.MX6 unimplemented or at least untested or am I doing something completely wrong here? Somebody here mentioned VCPU. I have not studied that concept yet. We have CONFIG_L4_VCPU=y Regards, Uwe Geuder Nomovok Ltd. Tampere, Finland uwe.gxuder(a)nomovok.com (bot test: humans correct 1 obvious spelling error)

2 3

Teaching OS Course notes
by teclis High Elf 17 Oct '14

17 Oct '14

Hi, I understand that Fiasco/L4Re is used as the teaching operating system at TU Dresden. Are there any course notes or lab notes available for courses at TU Dresden that used and/or covered Fiasco/L4Re? All the lab tutorials and course notes pertaining to the teaching operating systems used at MIT and Stanford are available online but I couldn't find anything similar for Fiasco. thanks

4 3

raw L4Task: Flash Access & Variable
by ba_f 16 Oct '14

16 Oct '14

Hello and thank u so far, >> Adam wrote: > It is possible. But of course there needs to be a driver for your flash > and a filesystem (if needed). And there's none. > There's a tmpfs, i.e. a filesystem that can store files, however, not > across reboots. Maybe that helps you already? Yes, volatile storage would do the trick. Unfortunately, i need some help here, too. :( I've found a post from Adam, concerning tmpfs: http://os.inf.tu-dresden.de/pipermail/l4-hackers/2014/006244.html I did all it says, and of course edited anything to my concerns. But my App fails to write at /tmp. fopen("/tmp/file", "wb") == NULL Maybe i do not place the fstab-file correct. Right now, fstab is located in the MODULE_SEARCH_PATH. But building the image does also work if there is no such file. Running the image, there are no complaints about a missing fstab. Is this correct behaviour? I also added fstab to my modules.list, without success. So... Is there another way to check if fstab is loaded correctly, besides using fopen(). -------- Here my files (shorted): # fstab / /tmp tmpfs defaults # modules.list entry app-cfg kernel fiasco -serial_esc roottask moe rom/app.cfg module l4re module ned module app.cfg module fstab [...] module libmount.so module libl4revfs-fs-tmpfs.so # app.cfg ld:start( "rom/app", { FSTAB_FILE = "rom/fstab" }); # Makefile REQUIRES_LIBS = libmount libl4revfs-fs-tmpfs

1 1

[ASK] Basic L4Re
by Erry Pradana Darajati 13 Oct '14

13 Oct '14

Hello L4 Hackers I am working on a project with L4Re in Pandaboard for my College Final Project. And right now i am in a stuck. So far, i have already know how to boot, print and read from the serial port (UART3) of pandaboard. But i can't understand the fundamental / basic of L4Re itself. Like how to make a new program outside the main program of "hello" (i am using hello code all of this time to experimenting). And also how to access the memory of the host computer using L4Re code. Because the main goal of the project i am working on is be able to access the GPIO of Pandaboard. And also, is there is any way to recompile L4Re without recompiling all of the module it use. Because in my computer it took a time to recompile even the change is only a line of code Can anyone teach or show me how to make it ? Actually i already have read the documentation of L4Re, but i am still having a hard time understanding it. Thank you for any answer and feedback. -- *Regards,* *Erry Pradana Darajati | Student of Computer Engineering* *Politeknik Elektronika Negeri Surabaya / EEPIS, Indonesia*

2 1

L4 Bootsrap Fiasco Addr
by Wölfel, Tobias 10 Oct '14

10 Oct '14

Hello All, I am working on porting Fiasco.OC to openrisc (or1k), but are stucked at booting the kernel. The problem is that the addr in boot_info.kernel_start is pointing to the beginning of the bootsrap, and therefore it will not start the kernel. In startup.cc there is the mbi, mb_info and mb_mod, which I suppose is the place where the addr is coming from. But where is it set exactly? For or1k IMAGE_MODE is used. The output of the bootstrapping is at the end. Thanks a lot for the help, Tobias " Loading fiasco [0x1103000-0x1104000] [0x1104000-0x11040ac] [0x11040ac-0x112c340] [0x112c340-0x1134468] [0x1135000-0x1135a84] [0x1135a84-0x1136000] boot_info.kernel_start 100 Loading sigma0 [0x100000-0x107ff4] [0x108000-0x10c17c] Loading foo find kernel info page... found kernel info page at 0x1103000 Regions of list 'regions' [ 100, 1d403] { 1d304} Boot bootstrap [ 128ac, 1291e] { 73} Boot mbi [ 17000, 171ab] { 1ac} Root Multiboot info [ 1d058, 1d0af] { 58} Boot mbi [ 100000, 10c17b] { c17c} Sigma0 sigma0 [ 1100000, 11001d3] { 1d4} Root Module [ 1103000, 1135fff] { 33000} Kern fiasco API Version: (87) experimental Sigma0 config ip:00100344 sp:0001b040 Roottask config ip:00000000 sp:00000000 Starting kernel fiasco at 00000100 "

2 3

Thread synchronization with in the same address space
by teclis High Elf 10 Oct '14

10 Oct '14

I have two threads running in the same server. On thread handles incoming ipc messages from the clients in different address spaces and the other thread does the work. The thread handling the incoming ipc needs to pass an integer value to the worker thread. Could I synchronize them using int l4util_cmpxchg32 <https://os.inf.tu-dresden.de/L4Re/doc/group__l4util__atomic.html#gacb4a5e47…> (volatile l4_uint32_t <https://os.inf.tu-dresden.de/L4Re/doc/group__l4__basic__types.html#gac1d09f…> *dest, l4_uint32_t <https://os.inf.tu-dresden.de/L4Re/doc/group__l4__basic__types.html#gac1d09f…> cmp_val, l4_uint32_t <https://os.inf.tu-dresden.de/L4Re/doc/group__l4__basic__types.html#gac1d09f…> new_val) the worker thread could then check the value of dest to get the integer. Would the worker thread need to use an atomic read function when it reads the value of dest and if so which function would the worker thread use for the atomic read? thanks,

3 3

examples/libs/l4re/c++/shared_ds/ds_clnt.cc
by teclis High Elf 10 Oct '14

10 Oct '14

>From examples/libs/l4re/c++/shared_ds/ds_clnt.cc line 49 : L4::Cap<L4::Irq> irq = L4Re::Util::cap_alloc.alloc<L4::Irq>(); It seems this template name L4::Cap and the function name L4Re::Util::cap_alloc are a bit misleading or only designate a sub-set of the objects functionality. In this line you are not just requesting permissions but getting a Unix style file handle that you then use to issue commands to the server on line 92: irq->trigger(); Is my understanding correct? At line 49 you are opening L4 equivalent of a Unix style file handle for sending commands to a server and not requesting permissions or am I over simplifying. thanks

2 1

contiguous memory blocks and zero copy
by teclis High Elf 09 Oct '14

09 Oct '14

How does L4Re handle contiguous memory blocks? What are the system calls used to allocate and manage contiguous memory? Is it possible to do zero copy data transfer between drivers and if so how is it done in Fiasco (so in linux world you would say no copy_to_user() and copy_from_user() ) thanks,

3 2