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Fiasco.OC (rev. 40) Pandaboard support
by Stefan Kalkowski 07 Sep '12

07 Sep '12

Hi L4-hackers, recently I've tried to adapt Genode's Fiasco.OC-platform support to use the latest Fiasco.OC/L4Re subversion revision. When trying it on x86 I didn't run into any trouble. It worked "out of the box". But when it came to ARM, I got problems to boot Fiasco.OC on the Pandaboard in general (also when using plain Fiasco.OC/L4Re). I've debugged the problem down to Cpu::init_errata_workarounds(). The problem is that pandaboard's boot code initializes TrustZone, and triggers a configuration-disable signal beforehand. That leads to 'undefined instruction' exceptions, whenever one tries to write into the p15/c15-c0-1 debug register (like it's done in init_errata_workarounds). The attached patch implements Cpu::init_errata_workarounds() empty for the pandaboard. Moreover, it restricts the appliance of ERRATA 743622 to CPU revisions: r2p0-r2p2. With the attached patch Fiasco.OC runs fine on the Pandaboard too. Best regards Stefan -- Stefan Kalkowski Genode Labs http://www.genode-labs.com/ · http://genode.org/ Genode Labs GmbH · Amtsgericht Dresden · HRB 28424 · Sitz Dresden Geschäftsführer: Dr.-Ing. Norman Feske, Christian Helmuth

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l4linux filesystem under fiasco-ux
by Ryan Brown 27 Aug '12

27 Aug '12

So far I've been running l4linux in a virtual machine. I'd like to run it in fiasco.ux to compare performance. But if l4linux under ux has no access to hardware, how do I access the filesystem? Am I stuck with the initial ramdisk? Or is there some way to mount the host filesystem, or a part of it?

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Announcement: Genode 12.08 improves NOVA and ARM support
by Christian Helmuth 23 Aug '12

23 Aug '12

Today Genode Labs released the 4th anniversary version of the Genode OS Framework. Most notable are the NOVA microhypervisor platform improvements for x86 64bit, object-integrity protection, and centralized kernel-resource allocation in core as well as comprehensive support for the OMAP4 SoC used in the PandaBoard. A quick overview of all changes that come with version 12.08: - Base platforms - New base-hw platform for running the framework on bare ARM hardware - NOVA support for x86_64, object integrity protection, core-only kernel-resource allocation - New OMAP4 SoC device drivers - HDMI output - SD-card - USB HID - Networking - New FFAT-based file-system service - New TAR file-system service - Improved Noux runtime - New port of the Lynx web browser - Shell scripting support - 3rd-party libraries - New ports of openssl, pcre, expat - MPC, libgmp for x86_64 and ARM - lwIP updated to version 1.4.1-rc1 - New port of the lighttpd web server More details are described in the release notes http://genode.org/documentation/release-notes/12.08 Have fun with our new release -- Christian Helmuth Genode Labs http://www.genode-labs.com/ · http://genode.org/ · /ˈdʒiː.nəʊd/ Genode Labs GmbH · Amtsgericht Dresden · HRB 28424 · Sitz Dresden Geschäftsführer: Dr.-Ing. Norman Feske, Christian Helmuth

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Local APIC address and MSI address
by Chen Tian 22 Aug '12

22 Aug '12

Hi, According to Intel manual, local APIC address starts at FEE00000, which is overlapping with the MSI's address register. How does this actually work? Thanks.

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i.mx53 and fiasco.oc
by Nikolay Golikov 22 Aug '12

22 Aug '12

Hello. I trying to run fiasco.oc + l4re on freescale i.mx53qsb. And have some problems to do this. I using i.mx51 platform configuration with some changes. I changed addresses in src/kern/arm/bsp/imx/mem_layout-arm-imx.cpp: EXTENSION class Mem_layout { public: enum Virt_layout_imx53 { Timer_map_base = 0xef1ac000, Uart_map_base = 0xef1bc000, Watchdog_map_base = 0xef198000, Pic_map_base = 0xef200000, Uart_base = Uart_map_base, }; enum Phys_layout_imx53 { Device_phys_base_1 = 0x53f00000, Device_phys_base_2 = 0x0fffc000, Watchdog_phys_base = 0x53f98000, // wdog1 Timer_phys_base = 0x53fac000, // epit1 Uart_phys_base = 0x53fbc000, // uart1 Pic_phys_base = 0x0fffc000, }; }; And made some little changes in other source files. When I try to boot it, I see something like this: ## Booting kernel from Legacy Image at 70800000 ... Image Name: L4 Image #47 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 897192 Bytes = 876.2 kB Load Address: 71000000 Entry Point: 71000000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... L4 Bootstrapper Build: #47 �В�т. �а�в�г. 21 16:49:21 MSK 2012, 4.5.1 Scanning up to 1024 MB RAM Memory size is 512MB (Limited by Scan) (70000000 - 90000000) RAM: 0000000070000000 - 000000008fffffff: 524288kB Total RAM: 512MB mod04: 710c1000-710da540: hello mod03: 710a7000-710c0458: l4re mod02: 7106d000-710a6624: moe mod01: 71063000-7106c370: sigma0 mod00: 71015000-71062cac: fiasco Moving 5 modules to 71100000 with offset eb000 moving module 05 { 710c1000-710da540 } -> { 711ac000-711c5540 } moving module 04 { 710a7000-710c0458 } -> { 71192000-711ab458 } moving module 03 { 7106d000-710a6624 } -> { 71158000-71191624 } moving module 02 { 71063000-7106c370 } -> { 7114e000-71157370 } moving module 01 { 71015000-71062cac } -> { 71100000-7114dcac } Scanning fiasco Scanning sigma0 Scanning moe --init=rom/hello Relocated mbi to [0x7100f000-0x7100f0d6] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x70002000 Regions of list regions [ 70001000, 700019bf] { 9c0} Kern fiasco [ 70002000, 7005cfff] { 5b000} Kern fiasco [ 70090000, 7009e17b] { e17c} Sigma0 sigma0 [ 70140000, 701717d3] { 317d4} Root moe [ 70178000, 7018eec7] { 16ec8} Root moe [ 71000000, 710143ef] { 143f0} Boot bootstrap [ 7100f000, 7100f1d3] { 1d4} Root Multiboot info [ 71192000, 711c553f] { 33540} Root Modules Memory API Version: (87) experimental Sigma0 config ip:700900e0 sp:71013044 Roottask config ip:70140178 sp:00000000 Starting kernel fiasco at 70001000 Hello from Startup::stage2 Initialize page table It stops on line 151 src/kern/arm/gic.cpp: Io::write<Mword>(0, _dist_base + DIST_CTRL); where _dist_base is Pic_map_base. If I understand correctly tzic on i.mx53 and tzic on i.mx51 is equivalent. And second question: I do not understand for what purpose make pysical devices and sdram mapping in: src/kern/arm/bootstrap.cpp? // map sdram linear from 0xf0000000 for (va = Mem_layout::Map_base, pa = Mem_layout::Sdram_phys_base; va < Mem_layout::Map_base + (4 << 20); va += 0x100000, pa += 0x100000) map_1mb(page_dir, va, pa, true, false); // map sdram 1:1 for (va = Mem_layout::Sdram_phys_base; va < Mem_layout::Sdram_phys_base + (4 << 20); va += 0x100000) map_1mb(page_dir, va, va, true, true); map_hw(page_dir); And why afterwards devises on physical addresses are out of order?

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Local APIC cannot deliver MSI to CPU (Fiasco.OC) ?
by Chen Tian 22 Aug '12

22 Aug '12

I am trying to use MSI for my network card. After setting the MSI slot in the PCI configuration block based on Intel manual, I can confirm the interrupt is delivered to the processor's local APIC by looking at the IRR content in kernel debugger. The bit in IRR that reflects the vector I specified in MSI message is set to 1 by APIC. However, the interrupt handler installed at that vector is never invoked. Does someone have any idea on this? The priority does not seem to be the issue, because I checked the TPR, which was 0x80 when I entered kernel debugger and decreased to 0 when I press 'g'. The error status register is also zero in the kernel debugging mode, while there is a pending interrupt request as suggested by IRR. But the cpu just can't get the interrupt. Any suggestions? Thanks.

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Issues in l4re-snapshot-2012081219 for ARM
by Ivan Loskutov 17 Aug '12

17 Aug '12

Hello, I tried new l4re-snapshot-2012081219 and found the following issues for ARM target: 1. File bin/setup.d/04-setup has error in BeagleBoard and Pandaboard L4Re configs generation. Patch attached. 2. I get errors at startup on Pandaboard KERNEL-369098737: alignment error at da067a03 (PC: f001e0ec, SP: 6e72654b, FSR: 400001, PSR: 600001d3) KERNEL-369098737: alignment error at da067a03 (PC: f001e0ec, SP: ea00000f, FSR: 400001, PSR: 600001d3) KERNEL-369098737: alignment error at da067a03 (PC: f001e0ec, SP: ea00000f, FSR: 400001, PSR: 600001d3) KERNEL-369098737: alignment error at da067a03 (PC: f001e0ec, SP: ea00000f, FSR: 400001, PSR: 600001d3) I found that the error is caused by a init_errata_workarounds() call in Cpu ::init (src/kernel/fiasco/src/kern/arm/cpu-arm.cpp). If I comment this call, then kernel started and hello example worked. Error is occurred when called set_c15_c0_1() function. I have not solved this issue yet. -- Ivan Loskutov

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dma memory mapping
by Chen Tian 17 Aug '12

17 Aug '12

I'd like to allocate some physical memory for a device's DMA. Do I need to use some special flags in l4_task_map? Thanks.

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input signal
by gaober 17 Aug '12

17 Aug '12

hi >Why do you need the IRQ in L4Linux then? Who is driving the touchscreen? That >instance should handle the TS IRQ as well. in mag, the tsc-omap3.c gets the coordinate like this mag | l4evdev.c Ev[22]. D: OMAP_TSC/input0, T : 3, C : 0 , V: 1085 mag | l4evdev.c Ev[23]. D: OMAP_TSC/input0, T : 3, C : 1 , V: 701 I want to make the l4linux and android kown the coordinate. now i cat /proc/interrupts it shows 210: 32 l4 l4-uart 211: 0 l4 l4fbev Err: 0 when i touch the omap3530 screen , the l4fbev still shows 0. i think i didn't get the l4fbev interruput.then how can i get it? in l4fb.c, there is the function irqerurn_t event_interrupt(), but in my board it didn't perform.maybe it is the reson? thanks very much! _______________________________________________ l4android-dev mailing list l4android-dev(a)lists.l4android.org http://lists.l4android.org/mailman/listinfo/l4android-dev

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Call for Papers: System Software Verification Conference (SSV 2012)
by Toby Murray 17 Aug '12

17 Aug '12

[Note: Submission Deadline is 19 September 2012] 7th Systems Software Verification Conference (SSV 2012) November 28--30, 2012 Sydney, Australia http://www.ssv-conference.org/ *Scope Industrial-strength software analysis and verification has advanced in recent years through the introduction of model checking, automated and interactive theorem proving, and static analysis techniques, as well as correctness by design, correctness by contract, and model-driven development. However, many techniques are working under restrictive assumptions that are invalidated by complex embedded systems software such as operating system kernels, low-level device drivers, or microcontroller code. The aim of this workshop is to bring together researchers and developers from both academia and industry who are facing real software and real problems with the goal of finding real, applicable solutions. By “real” we mean problems such as time-to-market or reliability that the industry is facing. A real solution is one that is applicable to the problem in industry and not one that only applies to an abstract, academic, toy version of it. In this workshop we will discuss software analysis and development techniques and tools; this forum will serve as a platform to discuss open problems and future challenges in dealing with existing and upcoming systems-level code. Topics include, but are not restricted to: • Model checking • Automated and interactive theorem proving • Static analysis • Automated testing • Model-driven development • Embedded systems development • Programming languages • Verifying compilers • Software certification • Software tools • Experience reports *Submissions Submissions must be made electronically through the EasyChair system (https://www.easychair.org/conferences/?conf=ssv2012) until September 19th, 2012. Papers should be up to 15 pages in pdf format and formatted in EPTCS style. Additional details may be included in a clearly marked appendix, which will be read at the discretion of the program committee. All will be subject to peer review under normal conference standards. Experience reports and papers on work in progress are welcome as long as there is a clear contribution. Submissions which are based or discuss a non-trivial piece of software are required to make all those non-standard software parts available, which a referee may need, in order to check the claims of the submission. Submitted papers must not have previously appeared in a journal or conference with published proceedings and must not be concurrently submitted to any other peer-reviewed workshop, symposium, conference or archival journal. Any partial overlap with any such published or concurrently submitted paper must be clearly indicated. *Publication The proceedings will be published with EPTCS (http://eptcs.org) *Important Dates Abstract Submission: September 14, 2012 Paper Submission: September 19, 2012 Notification: October 19, 2012 Conference: November 28–30, 2012 *Location The workshop will be held in Sydney, Australia at NICTA NRL Laboratory. *Organization Organizing Committee and PC Chairs • F. Cassez, NICTA, Sydney, Australia • R. Huuck, NICTA and UNSW, Sydney, Australia • G. Klein, NICTA and UNSW, Sydney, Australia • B. Schlich, ABB Corporate Research, Ladenburg, Germany Program Committee • Cyrille Artho, AIST, RISEC, Japan • Stefan Berghofer, Secunet, Germany • Frédéric Boniol, ONERA, France • Alessandro Coglio, Kestrel, USA • Joe Hurd, Intel, USA • Stefan Kowalewski, RWTH Aachen University, Germany • Thomas Kropf, Robert Bosch GmbH & U. of Tübingen, Germany • Kim G. Larsen, CISS, Aalborg University, Denmark • Toby Murray, NICTA, Sydney, Australia • Jan Peleska, Verified Systems International GmbH and University of Bremen, Germany • John Regehr, University of Utah, USA • Natarajan Shankar, SRI, USA • Zhong Shao, Yale, USA • Konrad Slind, Rockwell Collins, USA • Jun Sun, National University of Singapore, Singapore The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.

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